Long distance data transmission systems use timing recovery techniques to derive a timing or clock waveform from a received data signal. Such techniques are not required for low data rate transmission within a localized system where the transmit and receive clock signals can be derived from a common clock source because the clock frequency and phase required for accurate interpretation of the received data is known. However, in high data rate applications, small differences in path length can lead to significant misalignments in phase.
For example, in high speed space switches used for switching packetized data, the path length between any given input and any given output depends on the connection configuration, and the connection configuration varies from switching event to switching event according to the switching paths that happen to be available at the time that the switching event occurs. Consequently, a serial ensemble of data packets arrives at a receive terminal with a known frequency but an unknown phase. Equipment connected to the receive terminal requires a local clock signal having both the correct frequency and the correct phase in order to demultiplex and process the received data properly.
Thus, a fast, reliable method and apparatus for aligning the phase of the local clock signal with the phase of the received data signal is required. The method and apparatus should require a very short time interval to achieve phase alignment since data cannot be reliably transmitted during the phase alignment interval and this limits the usable information capacity of the channel. The phase alignment should be accurate enough, and the jitter of the aligned clock signal should be small enough to ensure an acceptably low error rate. The apparatus should be monolithically integrable for cost reduction, should have a low sensitivity to component changes to ensure reproducibility in volume production, should require minimal trimming of components to minimize production labour content, and should operate properly over a wide frequency range for adaptability to a wide range of system designs.
Known methods for providing a clock signal which is phase-aligned with a received data signal include transmitting a clock signal with the data signal. This method is expensive because of the additional transmission channel which is required. The received data signal can be filtered to recover the clock signal, but this method requires a relatively long time interval to achieve phase alignment. Moreover, for some commonly used data coding schemes, such as non-return to zero (NRZ) coding, the data must be preprocessed before the clock signal can be recovered by filtering. Phase alignment methods which employ an analog Phase Locked Loop (PLL) to phase-align a local clock signal with a received data signal also require a relatively long time interval to achieve phase alignment. A self-timing monostable multivibrator can be used to generate a phase-aligned clock signal, but such multivibrators require individual circuit trimming and are sensitive to temperature and component variations.
In U.S. Pat. Nos. 4,773,085, 4,756,011 and 4,821,296, and in IEEE Journal of Solid State Circuits, Vol. 23, No. 2, p. 323-328, Robert R. Cordell discloses methods and apparatus for aligning the phase of a local clock signal with a received data signal in which the received data signal is oversampled to detect data transitions, and the samples are processed to determine an optimal local clock phase. In U.S. Pat. No. 4,839,907, Steven P. Saneski discloses a method and apparatus in which the received data signal is delayed, the delayed data signal is compared to the received data signal at prescribed transitions of a local clock signal, and one of the received data signal and the delayed data signal is processed according to the results of the comparisons. These methods and apparatus are complex and difficult to implement in high data rate systems.
In U.S. Pat. Nos. 4,623,805 and 4,637,018, Laurence P. Flora et al disclose a method and apparatus for fixing the phase of local clock signals with respect to a master clock signal. The method and apparatus employs feedback circuitry including a tapped delay line which provides a series of local clock signals having a progression of phases, an accurate constant delay for delaying the master clock signal by a predetermined desired amount, a phase comparator for comparing the delayed master clock with a selected one of the local clock signals, and a multiplexer for selecting one of the series of local clock signals according to the results of the phase comparison Unfortunately, this method and apparatus requires that the desired delay of the local clock be predetermined and constant. Consequently, this method and apparatus is not practical for use in high data rate packet switching applications in which the local clock phase may require adjustment for each individual data packet.